1. Field of the Invention
The invention relates to a charge pump circuit for generating a high voltage from a low voltage.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as EEPROM (Electrically Programmable Read Only Memory), for example, it is necessary to supply a high positive voltage (or a high negative voltage) higher than a power supply voltage to a memory cell. When a high voltage is necessary like this, a method of integrating a charge pump circuit in the device is generally employed.
FIG. 6 is a circuit diagram of a conventional charge pump circuit. This charge pump circuit boosts an input voltage Vin (=a power supply voltage VCC) inputted to an input terminal IN, and outputs a high voltage HV as an output voltage Vout from an output terminal OUT. N-channel type charge transfer MOS transistors T0 to TM (M is an arbitrary number) each having a gate and a drain short-circuited are connected in serial between the input terminal IN and the output terminal OUT. The connecting nodes of the charge transfer MOS transistors T0 to TM are referred to as nodes A to X, respectively.
One terminals of capacitor elements C1 to CM are connected to the nodes A to X, respectively. The other terminals of the capacitor elements C1 to CM are connected to an oscillator circuit (not shown), and a first clock signal CLK and a second clock signal *CLK (a signal in opposite phase to the first clock signal CLK) with constant frequencies are alternately supplied thereto. The second clock signal *CLK is a signal formed by inverting the first clock signal CLK at an inverter 100.
In the above structure, when the power supply voltage VCC is supplied to the input terminal IN and the first and second clock signals CLK and *CLK are supplied to the capacitor elements C1 to CM, the high voltage HV higher than the power supply voltage VCC is obtained as the output voltage Vout from the source (the output terminal OUT) of the MOS transistor TM in the last stage. When the number of stages of the charge pump circuit is supposed to be M, HV=(M+1)×VCC is established. However, the voltage loss of the charge transfer device MOS transistors T0 to TM is neglected.
The relevant technique is described in the Japanese Patent Application Publication No. 2006-229755, for example.
The output current Iout of the charge pump circuit having the above structure is expressed by an equation Iout=CfV. Here, C stands for the capacitance value of the capacitor elements C1 to CM, f stands for the frequency of the first clock signal CLK, and V stands for the power supply voltage VCC inputted to the input terminal IN. It is noted that all the capacitor elements C1 to CM have the same capacitance values. As seen from this equation, the output current Iout of the conventional charge pump circuit is proportional to the power supply voltage VCC. Therefore, when the power supply voltage VCC is sufficiently high, the output current Iout is outputted more than needs, resulting in a problem that power consumption increases in vain.